Merge pull request #86 from t123yh/master

AndiDittrich · web-flow · commit 8f145ce3e035 · 2019-12-24T15:42:15.000+01:00
Add Verilog highlighting support.
diff --git a/src/lang/index.js b/src/lang/index.js
@@ -50,4 +50,5 @@ export {typescript} from './typescript';
 export {vhdl} from './vhdl';
 export {visualbasic} from './visual-basic';
 export {xml} from './xml';
-export {yaml} from './yaml';
+export {yaml} from './yaml';
+export {verilog} from './verilog';
diff --git a/src/lang/verilog.js b/src/lang/verilog.js
@@ -0,0 +1,90 @@
+// ----------------------------------------------------------------------
+// This Source Code Form is subject to the terms of the Mozilla Public
+// License, v. 2.0. If a copy of the MPL was not distributed with this
+// file, You can obtain one at http://mozilla.org/MPL/2.0/.
+// --
+// Copyright 2016-2018 Andi Dittrich <https://andidittrich.de>
+// Copyright 2019 Yunhao Tian
+// ----------------------------------------------------------------------
+
+// Generic Rules/Regex
+import _language_common_rules from '../engine/generic-rules';
+import {generic} from './generic';
+
+// Verilog HDL Language
+// Author: [Yunhao Tian]
+// --
+export class verilog extends generic {
+
+    // language aliases
+    static alias(){
+        return ['verilog'];
+    }
+
+    setupLanguage() {
+
+        this.rules = [
+            // strings
+            _language_common_rules.dqStrings,
+
+            // directives
+            {
+                regex: /`\w*\b/g,
+                type: 'k4'
+            },
+
+            {
+                regex: /\[( *\d+(?: *\: *\d+) *)\]/g,
+                type: 'e3'
+            },
+
+            {
+                regex: /\b(for|generate|if|else|repeat|case|endcase|begin|end|ifnone)\b/g,
+                type: 'k1'
+            },
+
+            {
+                regex: /\b(output|input|inout|reg|wire|assign)\b/g,
+                type: 'k5'
+            },
+
+            {
+                regex: /\b(module|endmodule|always|function|endfunction)\b/g,
+                type: 'k2'
+            },
+
+            // keywords
+            {
+                regex: /\b(or|rpmos|tranif1|and|initial|rtran|tri|parameter|rtranif0|tri0|pmos|rtranif1|tri1|buf|endprimitive|integer|posedge|scalared|triand|bufif0|endspecify|join|primitive|small|trior|bufif1|endtable|large|pull0|specify|trireg|endtask|macromodule|pull1|specparam|vectored|casex|event|medium|pullup|strong0|wait|casez|pulldown|strong1|wand|cmos|force|nand|rcmos|supply0|weak0|deassign|forever|negedge|real|supply1|weak1|default|nmos|realtime|table|defparam|nor|task|disable|highz0|not|release|time|wor|edge|highz1|notif0|tran|xnor|notif1|rnmos|tranif0|xor)\b/g,
+                type: 'k0'
+            },
+
+            // slash style comments
+            _language_common_rules.slashComments,
+
+            // multi line comments
+            _language_common_rules.blockComments,
+
+            // numbers
+            {
+                regex: /-?\d*'s?d[0-9_xz]+\b/gi,
+                type: 'n1'
+            },
+            {
+                regex: /-?\d*'s?h[0-9a-f_xz]+\b/gi,
+                type: 'n2'
+            },
+            {
+                regex: /-?\d*'s?b[01_xz]+\b/gi,
+                type: 'n3'
+            },
+            {
+                regex: /-?\d*'s?o[0-7_xz]+\b/gi,
+                type: 'n4'
+            },
+            _language_common_rules.int,
+
+            _language_common_rules.brackets,
+        ]
+    }
+}
