Add AVX-512 accelerated hexlify for the no-separator path when
available. This processes 64 bytes per iteration using:

- AVX-512F, AVX-512BW for 512-bit operations
- AVX-512VBMI for efficient byte-level permutation (permutex2var_epi8)
- Masked blend for branchless nibble-to-hex conversion

Runtime detection via CPUID checks for all three required extensions.
Falls back to AVX2 for 32-63 byte remainders, then scalar for <32 bytes.

CPU hierarchy:
- AVX-512 (F+BW+VBMI): 64 bytes/iteration, uses for inputs >= 64 bytes
- AVX2: 32 bytes/iteration, uses for inputs >= 32 bytes
- Scalar: remaining bytes

Expected performance improvement over AVX2 for large inputs (4KB+)
due to doubled throughput per iteration.

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

Add NEON vectorized implementation for AArch64 that processes 16 bytes
per iteration using 128-bit NEON registers. Uses the same nibble-to-hex
arithmetic approach as AVX2/AVX-512 versions.

NEON is always available on AArch64, so no runtime detection is needed.
The implementation uses vzip1q_u8/vzip2q_u8 for interleaving high/low
nibbles into the correct output order.

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

Add SSE2 vectorized implementation that processes 16 bytes per iteration.
SSE2 is always available on x86-64 (part of AMD64 baseline), so no runtime
detection is needed.

This provides SIMD acceleration for all x86-64 machines, even those without
AVX2. The dispatch now cascades: AVX-512 (64+ bytes) → AVX2 (32+ bytes) →
SSE2 (16+ bytes) → scalar.

Benchmarks show ~5-6% improvement for 16-20 byte inputs, which is useful
for common hash digest sizes (MD5=16 bytes, SHA1=20 bytes).

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

Benchmarks showed SSE2 performs nearly as well as AVX2 for most input
sizes (within 5% up to 256 bytes, within 8% at 512+ bytes). Since SSE2
is always available on x86-64 (part of the baseline), this eliminates:

- Runtime CPU feature detection via CPUID
- ~200 lines of AVX2/AVX-512 intrinsics code
- Maintenance burden of multiple SIMD implementations

The simpler SSE2-only approach provides most of the performance benefit
with significantly less code complexity.

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

…sions

Replace separate platform-specific SSE2 and NEON implementations with a
single unified implementation using GCC/Clang vector extensions. The
portable code uses __builtin_shufflevector for interleave operations,
which compiles to native SIMD instructions:
- x86-64: punpcklbw/punpckhbw (SSE2)
- ARM64: zip1/zip2 (NEON)

This eliminates code duplication while maintaining SIMD performance.
Requires GCC 12+ or Clang 3.0+ on x86-64 or ARM64.

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

Extend the portable SIMD hexlify to handle separator cases where
bytes_per_sep >= 16. Uses in-place shuffle: SIMD hexlify to output
buffer, then work backwards to insert separators via memmove.

For 4096 bytes with sep=32: ~3.3µs (vs ~7.3µs for sep=1 scalar).
Useful for hex dump style output like bytes.hex('\n', 32).

Also adds benchmark for newline separator every 32 bytes.

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

Lower the threshold from abs_bytes_per_sep >= 16 to >= 8 for the SIMD
hexlify + memmove shuffle path. Benchmarks show this is worthwhile for
sep=8 and above, but memmove overhead negates benefits for smaller values.

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

GCC's vector extensions generate inefficient code for unsigned byte
comparison (hi > nine): psubusb + pcmpeqb + pcmpeqb (3 instructions).

By casting to signed bytes before comparison, GCC generates the
efficient pcmpgtb instruction instead. This is safe because nibble
values (0-15) are within signed byte range.

This reduces the SIMD loop from 29 to 25 instructions, matching the
performance of explicit SSE2 intrinsics while keeping the portable
vector extensions approach.

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

Extract the scalar hexlify loop into _Py_hexlify_scalar() which is
shared between the SIMD fallback path and the main non-SIMD path.
Uses table lookup via Py_hexdigits for consistency.

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

Extend portable SIMD support to ARM32 when NEON is available.
The __builtin_shufflevector interleave compiles to vzip instructions
on ARMv7 NEON, similar to zip1/zip2 on ARM64.

NEON is optional on 32-bit ARM (unlike ARM64 where it's mandatory),
so we check for __ARM_NEON in addition to __arm__.

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

Add targeted tests for corner cases relevant to SIMD optimization:

- test_hex_simd_boundaries: Test lengths around the 16-byte SIMD
  threshold (14, 15, 16, 17, 31, 32, 33, 64, 65 bytes)

- test_hex_nibble_boundaries: Test the 9/10 nibble value boundary
  where digits become letters, verifying the signed comparison
  optimization works correctly

- test_hex_simd_separator: Test SIMD separator insertion path
  (triggered when sep >= 8 and len >= 16) with various group
  sizes and both positive/negative bytes_per_sep

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>